1. Technical Field
One or more embodiments of the present invention relate to an efficient utilization of memory in a digital filter.
2. Background Art
Digital processing is widely used in various types of signal processing and various types of digital filters are used.
FIG. 2 shows a first-order IIR filter as an example of a digital filter. An input signal In is multiplied by a coefficient a at a coefficient multiplier 10 after which a·In is input by an adder 12. The input signal In is delayed by a delay circuit 14, multiplied by a coefficient b at a coefficient multiplier 16, then input as b·Z1 by the adder 12.
An output of the adder 12 is output as an output signal Out and also delayed by a delay circuit 18, multiplied by a coefficient c at a coefficient multiplier 20, then input as c·Z2 by the adder 12.
Therefore, an operation of Out=a·In +b·Z1+c·Z2 is performed at the digital filter.
Here, coefficient data a, b, c and delay data Z1, Z2 are stored in memory (RAM), such as SRAM, and read therefrom. On the other hand, the operations of (1) a·In, (2) b·Z1, and (3) c·Z2 are performed for the abovementioned operation in one clock cycle. Thus, it is necessary for the coefficient data and the delay data to be respectively read simultaneously.
In this sort of instance, operational efficiency is better in a configuration having separate RAM units where the coefficients a, b, c are stored into a coefficient RAM and the delay data Z1, Z2 are stored into a delay RAM.
Here, when implementing the digital filter in hardware, there is often a restriction (capacity restriction) in the minimum value of RAM capacity. Namely, the RAM is a general-purpose storage member and the use of readily available RAM as a general-purpose circuit is unavoidable because the cost becomes high if one is fabricated for a special purpose. Accordingly, there may be instances where the coefficient RAM and the delay RAM have a capacity larger than necessary.
As a solution, one method uses a dual port SRAM, which is a single RAM capable of being simultaneously read from two ports. However, the dual port SRAM has a large area, which is inefficient, compared to a single port SRAM having the same capacity.